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Digital Design & Simulation

Applying AssertionBased Formal Verification to Verification Hot Spots

Based on our experience helping many design teams deploy assertions and formal verification, we recommend deploying ABV (including formal model checking) on the most salient verification hot spots in a design, following a sevenstep, formal verification planning process. By focusing ABV on verification hot spots, a design team can adopt ABV incrementally as they continue to use their simulationbased methodology. This has the added benefit of minimizing the risks involved with adopting a new methodology while maximizing the returnoninvestment.

Custom Design & Simulation

Port Impedance and Admittance Modeling Using Eldo and Eldo RF

This application note was written for those who need a Thevenin or Norton equivalent circuit (i.e. resistorcapacitance, resistanceinductance, conductancecapacitance or conductanceinductance) of a port impedance or admittance, respectively. This may happen if a block designer does not want to include the netlist of a given block in a simulation, but would still like to get realistic models of the load and/or source. Using a lumped element equivalent of a port impedance or admittance can also be useful to analyze stability issues (tracking a node impedance variation over frequency). Yet another example would be to maximize an impedance in a tank circuit, in order to maximize voltage swing.

The document is organized in 8 short sections, each section showing sample netlist code. Sections 1 and 2 deal with port impedance modeling using smallsignal (AC) analysis, and largesignal analysis (SST), respectively. Sections 3 and 4 describe the equivalent case of admittance modeling. In sections 5 and 6, previous results are applied to the case of a low noise amplifier (LNA). Particularly, it is shown how largesignal Z or Y parameters relate to smallsignal parameters at low input levels.

Finally, sections 7 and 8 show how to use Sparameter files, to take into account the dependence on the frequency.

Verification of RadioFrequency Transceivers

The global market for portable communication products such as pagers, twoway radios, cordless phones, cellular phones, personal GPS receivers, wireless internet browsers, and portable video phones is growing at a rapid pace. These small wireless handsets carry voice, data, image and video, and will revolutionize the way people

Noise Considerations in Circuits and Systems

Sources of noise in analog ICs, and the methods used to calculate the effects of this noise on larger system performance. While many articles take the viewpoint of the engineer who wants to design a lownoise amplifier with either discrete transistors or ASIIC cells, this paper focuses on standard but nonideal packaged parts. It offers a concise way to calculate the noise performance of a device or system. The result is an easy to use reference for the engineer who needs to know the effect of nonideal ICs on overall system performance. The examples include data sheets of commercially available IC operational amplifiers.

IEEE Std VHDL 1076.11999: The Analog and MixedSignal Extensions for VHDL

Analog and mixedsignal designers have long lacked what their digital colleagues have enjoyed for a decade: standard hardware description languages that allow portability of models between different EDA tools. At last the effort to add analog and mixedsignal modeling to the IEEE standard language VHDL is bearing fruit. The new standard language for analog and mixedsignal design, VHDLAMS, won the approval of voting IEEE members and passed the final hurdles of the IEEE standardization process in the spring of 1999. Several commercial and academic implementations of the language are now available. Here are the reasons the effort was worthwhile, along with a brief review of who is making and using VHDLAMS software, and a taste of what it is like to code models in VHDLAMS.

MixedSignal ASIC TopDown and BottomUp Design Methodologies using VHDLAMS

The paper describes the process of topdown and bottomup of a mixedsignal ASIC design using VHDLAMS. The first part of the paper, introduced by Mr. Jean Oudinot, the topdowm and bottomup approaches supported by ADVance MS?, a new MixedSignal simulation environment from Mentor Graphics (MGC). The second part is contributed by Mr. Michel Robbe and Mr. Patrick Radja from Matra Nortel Communications (MNC). They describe how they validaded the new design methodologies with a demonstrator: a Single Conversion Receiver (superheterodyne). The process starts from system specification and simulation at the toplevel abstraction all the way down to IC layout and verification. The simulation results of the system were compared successfully to the actual measurements.

Common Rail Injection System described in VHDLAMS and Simulated with ADVance MS

In this paper, we present a Common Rail injection system developed using VHDLAMS language [1] within TOOLSYS project [3]. This system enables the control of the fuel quantity that is injected in the cylinders of a Diesel engine. The description of the system is based on a top down methodology associated to a bottom up one. The bottom up methodology is used for describing models, dedicated for control designs that need a high degree of details and the top down one is used for abstract models. The overall engine control system, which is a relevant application to the automotive industry, has been simulated in ADVance MSTM[4], a tool developed by Anacad/Mentor Graphics

A unified approach of PM noise cancellation in large RF multitone autonomous circuits

This paper presents a simulation method to compute noise in autonomous and forced circuits using the Harmonic Balance (HB) formulation. Thanks to iterative linear solvers and multidimension conversion matrices, it can handle large multitone circuits to calculate phase noise spectra near and far from the carrier frequency. Its efficiency is illustrated with two real circuits.

Simulation Method to Extract Characteristics for Digital Wireless Communication Systems

In all wireless standards involving digital modulation, new fundamental characteristics have to be extracted for quantifying the linearity/distortion in RF designs. This paper describes a simulation technique, Modulated Steady State, and its use to extract these specifications. An example of its application to a typical RF transmitter with a p/4DQPSK modulator is presented.

Modeling of Timing Jitter in Oscillators

Timing jitter in oscillators is a key factor determining the phase noise performance of phaselocked loops. This paper reviews the theory of phase noise in oscillators, and presents timing jitter models suitable for discrete event simulation of these systems.

Introduction to ADMS RF (Digital AGC Loop)

The objective of this technical paper is to provide an introduction to ADVance MS RF (abbreviated to ADMS RF in the rest of this text), using an example wherein the tool brings real benefits in terms of performance and usability.

Many digital communication systems include tightly integrated radio frequency (RF), analog/mixedsignal and DSP functions, which causes difficulties with classical transient simulation, because of the RF carriers.

ADMS RF specifically targets specifically these types of challenging simulations. It is basically an advanced simulation technique, leveraging the power of ADVance MS and the efficiency of the modulated steadystate algorithm in Eldo RF. ADVance MS and Eldo RF are respectively the analog/mixedsignal and RF simulators from Mentor Graphics.

This technical paper shows how ADMS RF can be used to efficiently simulate an automatic gain control (AGC) loop. The system is driven with a digitally modulated signal (GMSK). The different blocks in this loop are described in SPICE (transistorlevel), VerilogA (behavioral), and VHDL. The gain control is performed digitally.

Getting Closer to a TopDown Methodology for RF SoC Design

The drive to fully integrate communication products onto a single chip has created the urgent need for an integrated RF SoC design flow. Until now the EDA community has not managed to assemble a satisfactory integrated flow for mixedsignal RF because no single vendor has offered all the necessary technologies. Vendors have tried to use cosimulation to achieve this, but cosimulation seriously complicates the designer's life even preparing the design for simulation is far harder this way and cosimulation is intrinsically slower, less stable and subject to conflicting clock problems. Even if you have all the technologies, integrating them into a single kernel solution is an enormous task, which Mentor Graphics engineers have been working on for about seven years. The good news is that an integrated single kernel solution is now available.

As today's mixedsignal SoC designs continue to increase in complexity, functional verification methods are rapidly evolving. Now more than ever, new, more efficient methods of verification must be explored and adopted in order to keep up with the growing demands of SoC design.

Historically, entire designs were represented by a single set of transistorlevel schematics, with each individual component, as well as the entire design itself, being functionally verified using a digital gatelevel and or analog transistorlevel simulator. In today's SoC designs, the necessity to incorporate reusable IP from multiple sources requires that both VHDL and Verilog modeling languages must be supported in the simulation environment. To efficiently address this requirement, functional verification must now take place in a single kernel simulation environment, with the ability to trace simulation results back to appropriate source code line in Verilog or VHDL. Additionally, there must be a means by which to cosimulate sensitive analog functions using traditional SPICE and advanced analog RF algorithms. There are also the emerging standard analog and mixedsignal functional modeling languages VHDLAMS (IEEE 1076.1), Verilog A, and VerilogAMS. These languages are becoming popular as alternatives to the traditional means of drawing transistorlevel schematics to enter analog and mixedsignal types of components.

Inductor Device Generators for Automation of RF IC Design

Today's mixedsignal RF IC designs present many challenges and require an integrated, easytouse design and verification flow. One of the primary challenges is postlayout verification, where many physical effects impact the quality and performance of the complete design. In situations where rapid pre to postlayout turnaround is key to meeting project deadlines, new scenarios must be investigated to increase productivity, and tradeoffs must be made during the design and verification process.

In this article, we will introduce new inductor device generators, which offer dramatic efficiency increases in the development and automation of RF IC design, layout creation and verification. The flexibility and easeofuse of these device generators, which fit into the Mentor Graphics AMS SoC Design Flow, make them very attractive to any RF IC Designer.

Bluetooth Transceiver Design with VHDLAMS

This paper describes the design challenges of BlueTraC, a lowcost, lowpower radio transceiver and the usage of mixedsignal/mixedmode techniques and behavioral modeling with ADVance MS (ADMS) from Mentor Graphics to address and solve them. BlueTraC from Spirea is a Bluetooth 1.1 compliant Class 2 radio transceiver. In addition to all the required RF and analog functions, the chip also includes a complete digital GFSK modem, making it a very complex mixedsignal (MS) systemonchip (SoC). VHDLAMS, the mixedsignal IEEE 1076.1 standard modeling language, was used to describe the SoC building blocks at different levels of detail and complexity. This permitted us to perform top level functional verification and debugging, as well as detailed subsystem simulations throughout the design process. We are presenting the concept and the results we obtained, in terms of performance and accuracy. The methodology that we deployed increased the confidence in silicon success and allowed on time delivery.

Efficient Simulation Techniques for Modulated DeltaSigma FractionalN Synthesizers

In this technical paper, we show an efficient simulation methodology for the analysis of spurs in a fractionalN deltasigma PLL. Deltasigma PLLs can be used for frequency synthesis or even direct modulation, typically for GMSK or GFSK. The simulators used are Eldo, Eldo RF and ADMS RF.

A deltasigma PLL is an attractive solution for agile frequency synthesis or even direct modulation. This architecture indeed can meet requirements such as lowpower consumption and simple topology, and is suitable for highlevel integration.

The goal is to analyze the possible reasons for the presence of said fractional spurs in the output spectrum of a fractionalN deltasigma PLL for wireless applications, and to show how this can be efficiently simulated.

Modeling and Simulating a ZigBee Wireless Transmitter Path using ADMS RF

Today's high technology marketplace demands more capability and reliability from wireless technologies, especially lowcost and lowpower wireless communications with relatively low data rates. These types of applications are used in home automation systems, games and automotive controls, and the requirements for these radio transceiver systems make a highlyintegrated CMOS implementation an obvious choice. The ZigBee wireless technology and its underlying IEEE 802.15.4 standard is an ideal lowcost, lowpower wireless solution.

Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning

Capturing the designer's intent during floorplanning plays a critical role to improve design productivity of systemsonchip (SoC). This paper presents a design technique which helps manage changes very late in the design process caused by the concurrent implementation of blocks in a hierarchical layout.

We developed a floorplan description language and associated a methodology to capture the actual designer's intent for block placement, soft macro shaping, JTAG cell placement, power grid and power rings design.

The concept allows reuse of the description and therefore fast iterations during incremental changes at the top level or at the block level. This technique can accommodate changes very late in the design process by removing tedious manual adjustment of the hierarchical layout.

This approach has successfully been applied on a complex SoC and IP block implementation .It has demonstrated a reduction from one day to few minutes for a floorplan iteration, crucial in a concurrent design environment where asynchronous changes in the blocks require to constantly revisit the top level layout and vice versa.

Validation of a New Methodology using VHDLAMS on a Harddisk Drive Design

The paper describes the validation of a new methodology using VHDLAMS on a STMicroelectronics harddisk drive read/write channel design called "Giotto". The new mixedsignal simulation environment ADVance MS supporting multilanguage from Mentor Graphics was used. The objective was to compare the new development of a known circuit designed by current tools. The results showed clearly the great benefice of VHDLAMS over the former proprietary language HDLA, and ADVance MS over EldoVerilog. The speed performance gain was over 90%. Also developing models with VHDLAMS was much easier and more efficient. This new methodology is now ready to be adopted by ST for their new generation harddisk designs.

Power Amplifier Simulations with Eldo RF(ACPR)

As engineers condense more functionality onto integrated circuits because of deep submicron technologies, systemonchip designs have become a widespread reality. However, even though processing technology now can support ICs that incorporate millions of transistors, traditional power analysis tools lag far behind, unable to handle the sheer size of these designs.

To close this gap, Mentor Graphics developed Mach PA, a new power analysis tool for circuit simulation up to 1,000 times faster than traditional SPICE. Using innovative, proprietary algorithms, Mach PA delivers the superior speed, accuracy and capacity needed for determining whether a SOC IC design meets detailed power specifications. Now, designers can efficiently perform transistorlevel power analysis for even the largest and most demanding SOC designs.

Mentor Graphics AnalogMixedSignal IC Design Kits Save Time and Improve Design Accuracy

Creating a custom IC or analog/mixedsignal design environment is a very timeand resourceconsuming initiative, yet design teams are constantly facing mounting pressure to shorten timetomarket. Acquiring all the necessary simulation models and rule files from the foundry and integrating them into the development environment can take manmonths and significantly lengthen a development project. A significant amount of the work involves ensuring consistency among the models
and rule files to reduce risk of design failure, and most of this work must be complete before the design process can begin.

PhaseLocked Loop Simulation with Modulated SteadState Analysis

Currently, a PhaseLocked Loop remains one of the more difficult designs to characterize; the transient simulation used is a large time consumer. The time step used for the simulation is given by the Radio Frequency (RF) signal provided by the VCO that could be 1000 times greater than the low frequency signal (i.e. reference clock).

A Fully Automated Approach for Analog Circuit Reuse

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then produces a resized design in the target technology with the same performance as the original design. The migration of a low voltage Delta Sigma modulator is presented in this paper to validate the migration engine.

PostLayout Analysis with Eldo and Eldo RF

It is important to verify the behavior and interaction of digital, analog and RF circuitry together in the presence of layout parasitics. This also means being able to debug the design in the presence of parasitics, and mastering large amounts of parasitic data. An approach is presented which allows the design engineer to use Eldo? and Eldo RF to achieve the best combination for accuracy, performance and debugging.

Bluetooth Transceiver Design: A TopDown Flow for Complex RF MixedSignal ICs

This paper describes the design challenges of BlueTraCTM, a lowcost, lowpower radio transceiver. It details how a topdown methodology along with mixedsignal/mixedmode techniques and behavioral modeling can be used to effectively address and solve the design challenges of this complex RF mixedsignal IC. The methodology leverages an outofthebox design flow from Mentor Graphics that includes Design ArchitectIC for design entry and simulation control, ADVance MS (ADMS) for singlekernel mixedmode simulation, IC Station for schematicdriven physical layout, and Calibre for physical verification and extraction.

Port Impedance and Admittance Modeling Using Eldo and Eldo RF

This application note was written for those who need a Thevenin or Norton equivalent circuit (i.e. resistorcapacitance, resistanceinductance, conductancecapacitance or conductanceinductance) of a port impedance or admittance, respectively. This may happen if a block designer does not want to include the netlist of a given block in a simulation, but would still like to get realistic models of the load and/or source. Using a lumped element equivalent of a port impedance or admittance can also be useful to analyze stability issues (tracking a node impedance variation over frequency). Yet another example would be to maximize an impedance in a tank circuit, in order to maximize voltage swing.

The document is organized in 8 short sections, each section showing sample netlist code. Sections 1 and 2 deal with port impedance modeling using smallsignal (AC) analysis, and largesignal analysis (SST), respectively. Sections 3 and 4 describe the equivalent case of admittance modeling. In sections 5 and 6, previous results are applied to the case of a low noise amplifier (LNA). Particularly, it is shown how largesignal Z or Y parameters relate to smallsignal parameters at low input levels.

Finally, sections 7 and 8 show how to use Sparameter files, to take into account the dependence on the frequency.

PostLayout Analysis with Eldo and Eldo RF

The document is organized in 8 short sections, each section showing sample netlist code. Sections 1 and 2 deal with port impedance modeling using smallsignal (AC) analysis, and largesignal analysis (SST), respectively. Sections 3 and 4 describe the equivalent case of admittance modeling. In sections 5 and 6, previous results are applied to the case of a low noise amplifier (LNA). Particularly, it is shown how largesignal Z or Y parameters relate to smallsignal parameters at low input levels.

Finally, sections 7 and 8 show how to use Sparameter files, to take into account the dependence on the frequency.

Verification of RadioFrequency Transceivers

The global market for portable communication products such as pagers, twoway radios, cordless phones, cellular phones, personal GPS receivers, wireless internet browsers, and portable video phones is growing at a rapid pace. These small wireless handsets carry voice, data, image and video, and will revolutionize the way people communicate and access information. Manufacturers of these highperformance communication systems must compete on the basis of power consumption, cost, size, weight and features. The radiofrequency (RF) transceiver is the critical hardware that dictates the performance, as well as the cost, the size and the useful battery life in a portable handheld communication product. However, design and verification of the RF transceiver can be difficult or impossible without the right tools.

VCO Simulations with Eldo RF (tuning range and phase noise)

Eldo RF can be used for the analysis of a Voltage Controlled Oscillator (VCO) for RF applications such as GSM and DCS 1800. The chosen VCO is realized in a standard CMOS technology. We show how to setup simulations that allow you to analyze the tuning range of the VCO, to extract its phase noise, and to carry miscellaneous parametric simulations. Readytorun netlists are associated with the application note, to illustrate the simulations. The analysis of autonomous circuits such as oscillators and VCOs is part of the 5.3 release of Eldo RF; thus the required release level to run the provided netlists is 5.3

Noise Considerations in Circuits and Systems

Sources of noise in analog ICs, and the methods used to calculate the effects of this noise on larger system performance. While many articles take the viewpoint of the engineer who wants to design a lownoise amplifier with either discrete transistors or ASIIC cells, this paper focuses on standard but nonideal packaged parts. It offers a concise way to calculate the noise performance of a device or system. The result is an easy to use reference for the engineer who needs to know the effect of nonideal ICs on overall system performance. The examples include data sheets of commercially available IC operational amplifiers.

IEEE Std VHDL 1076.11999: The Analog and MixedSignal Extensions for VHDL

Analog and mixedsignal designers have long lacked what their digital colleagues have enjoyed for a decade: standard hardware description languages that allow portability of models between different EDA tools. At last the effort to add analog and mixedsignal modeling to the IEEE standard language VHDL is bearing fruit. The new standard language for analog and mixedsignal design, VHDLAMS, won the approval of voting IEEE members and passed the final hurdles of the IEEE standardization process in the spring of 1999. Several commercial and academic implementations of the language are now available. Here are the reasons the effort was worthwhile, along with a brief review of who is making and using VHDLAMS software, and a taste of what it is like to code models in VHDLAMS.

MixedSignal ASIC TopDown and BottomUp Design Methodologies using VHDLAMScontributed by Mr. Michel Robbe and Mr. Patrick Radja from Matra Nortel Communications (MNC). They describe how they validaded the new design methodologies with a demonstrator: a Single Conversion Receiver (superheterodyne). The process starts from system specification and simulation at the toplevel abstraction all the way down to IC layout and verification. The simulation results of the system were compared successfully to the actual measurements.