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Class Description and Learning Objectives
Bottom line: you'll learn to design, build, and debug printed-circuit-boards.

Longer story: In the past building prototypes of electronic components for new projects/products was limited to using protoboards and wirewrap. Manufacturing a printed-circuit-board was limited to final production, where mistakes in the implementation meant physically cutting traces on the board and adding wire jumpers - the final products would have these fixes on them! Today that is no longer the case, while you will still cut traces and use jumpers when debugging a board, manufacturing a new final version without the errors is a simple and relatively inexpensive task. For that matter, manufacturing a prototype printed circuit board which you know is likely to have errors but which will get the design substantially closer to the final product than a protoboard setup is not only possible, but desirable.

Inexpensive prototyping of PCB's allows you to go through multiple revisions, incrementally increasing the complexity (reducing the size, increasing the layer count, etc) without the worry of only being able to manufacture once. This process provides many benefits to both the worlds of research and industry, as the design of avionics can proceed faster and with lower costs. That is why the class will teach you how to design PCB's.

Schedule overview. WEEK # TOPICS
1-5 Electronics review
6-7 Schematics

Documentation

8 Electronics review (cont.)

Schematics (cont.)

PCB's

Assembly and debug

Documentation (cont.)

9-11 PCB's (cont.)
12-13 Assembly and debug (cont.)
14 Assembly and debug (cont.)

Documentation (cont.)

Assignments, Projects, and Grading
The first half of the class will utilize problem sets based on the introductory material. The second half will be based on projects which demonstrate the ability to produce an avionics prototype board. The following are the deliverables for this class:

Problem Sets
Four problem sets during the first month of class to demonstrate the ability to identify essential electronic components
While students can work in groups to discuss the problem sets, each student is expected to turn in their own solutions
Project
Detailed schematic
Documentation on the operation of the circuit
PCB layout
Report documenting their experience and results during testing and debugging
Depending on class registration and the availability of software licenses, the projects will be worked either individually or in groups of at most three students, preferably two. When the work is performed in groups, the schematic, functional documentation, and layout will be shared deliverables, while the experiences and debugging report will be turned in individually. Teradyne Announces Debug Pro? Test Programming and Debug Software for TestStation In-Circuit PCB Testers
Business Wire, Nov 14, 2006 Tags: programming, software, Teradyne Inc.

E-mail Print Link Enhanced Graphics and Simplified, Menu-Driven Programming Ensures a Simpler, More Intuitive Interface and Easier Access to TestStation's Powerful Suite of Test Debug Tools

NORTH READING, Mass. -- Teradyne (NYSE: TER), the world's leading ATE manufacturer of in-circuit test equipment, today announced Debug Pro, a new user-friendly software debug environment for TestStation[TM] ICT equipment. Debug Pro features a more intuitive graphical user interface and provides users with more comprehensive tools, simplified command menus, and operational displays for better debugging and qualifying in-circuit test programs. With Debug Pro, users can better leverage TestStation's powerful programming and test capabilities. Key elements of Debug Pro include:

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Getting Started with e-Learning: Eight Questions to Consider * A Label Navigator that graphically displays each of the program's tests. Common resistor, capacitor, inductor and other user-defined tests are automatically grouped using folders. Status icons more clearly indicate the Pass/Fail status of each test. Operators can select individual debug tests by simply clicking on menus or by using new built-in search capabilities.

* A Statement Editor that displays each of the specified parameters available in user-selected tests and allows operators to easily select and modify those parameters using the mouse or keystrokes. Its configurable editor can be set to display only the test parameters that operators commonly modify during debug activities.

* A Guard Editor window that displays the test instrument connections and relevant in-circuit interconnections associated with each device under test. Operators can more easily add and remove test guard points using their mouse.

* A Charting Tool that displays measurement results using run or histogram charts and reports test statistics such as Mean, Std Deviation, Cp, and Cpk. Operators can acquire and view charts quicker to determine the reliability of all test measurements.

* A Component and Property Information windows that display more helpful information about board components, nets and other tester resources.

* A Customizable Tool Bar that provides greater access to comprehensive debug tools, including board and schematic viewers, data collection charts, vectorless test programming and test quality tools.

* An optional Untranslator Window provides experienced users with the ability to perform debug activities using the familiar commands and keystrokes of legacy Runtime debug environments.

"Our early adopter audits and performance benchmarks show that Debug Pro's intuitive operation and advanced capabilities can effectively help operators complete their debug activities faster with higher quality results," said Alan Albee, product line manager for TestStation products. "Debug Pro simplifies typical debug sequences and provides quicker access to TestStation's rich debug techniques and test tools so that operators can concentrate on better solving their specific PCB testing challenges."
Who we are Digital-to-Analog (DAC) Hi-Fi stereo converter modules and their applications.
CONTACT - To contact us you can use this online form or the contact information provided on this page.
LINKS - Collection of electronics reference information, calculators, links to electronics magazines, component search engines and leading component manufacturers.

What can Pronine Electronics Design do for you?

We provide out-sourced engineering services for the growing number of companies that consider it impractical to maintain their own full-time designer teams in all related areas of expertise. And for those who just need additional resourses to speed up their development process.
We seek to establish long term business relationships with our clients, though one-time jobs are also welcomed.
We can help you with electronic product development or specialized research equipment design starting from concept or at any other stage of the development process. We also can "take a sad song and make it better" meaning that we can help you to improve, debug, update, modify, adapt or optimize your existing design or electronic equipment. Printer-Friendly Version

Highest Quality In-Circuit Test

Teradyne’s TestStation? family of In-Circuit Test Systems provides high volume electronics manufacturers with reliable high-quality test for the latest PCB technologies. Configurable from 256 to 7680 test pins, the TestStation product family provides the highest-capacity in-circuit test solution on the market.

Featuring SafeTest protection technologies and a turnkey test programming environment, the TestStation systems allow direct transfer of test programs and fixtures from all 228X and TestStation in-circuit testers without extra costs or further program development.

Comprehensive Fault Detection

Unpowered test capabilities for TestStation systems include shorts, vectorless opens, and analog value testing. Powered-up test capabilities include digital device vector testing, reduced access boundary scan testing, high speed FLASH and ISP device programming, frequency and time event measurements, synchronized mixed signal device testing, and functional cluster testing. These tests can be automatically generated using Teradyne’s D2B CAD preparation software and automatic test generation software or manually created using a simple, but powerful test programming language.

Teradyne’s advanced test quality software analyzes the test program and generates reports to show overall test fault coverage and unreliable tests that require additional debug.

Accurate, Reliable, and Safe Electrical Test

The strength of TestStation in-circuit testers lies in their ability to perform accurate, reliable, and safe powered-up testing. Patented SafeTest technologies like per pin programmable logic levels, backdrive current, and backdrive duration thresholds ensure potentially harmful voltage and currents are not applied to the board during device testing (even if the board is defective).

Multi-level digital isolation software automatically isolates device outputs on any nets being driven. This minimizes backdrive conditions and prevents potentially harmful voltage spikes that can occur when backdriven outputs suddenly change logic state. The specialized digital controller quickly executes test vectors to minimize the duration of backdrive currents and reduce the opportunity for voltage spikes that can occur from on-board activities.

For technical information on the benefits of Teradyne's Backdrive Current Sensing capabilities, refer to this paper...

Exceptional Diagnostic Accuracy and Test Throughput

TestStation provides excellent diagnostic accuracy because the closed-loop, low-impedance driver remains accurate even under fault conditions. Additionally, the unique programmable backdrive measurement and control capabilities of the TestStation can detect faults such as faulty enable pins and marginal output transistors that can not be detected on other in-circuit testers.

Patented diagnostic algorithms like SoftProbe, BusBust, and Adaptive Patterns are designed to minimize unnecessary board repairs and eliminate false failure reports.Cambridge Technology Group
PROFILE PRODUCTS / SERVICES NEWS JOBS EVENTS
Date: 30/10/07
XJTAG v2.0 boundary scan system sets new standard for PCB debug and test
XJTAG, a leading supplier of IEEE Std. 1149.1 compliant boundary scan development tools, today announced version 2.0 of its popular XJTAG boundary scan development system, which sets a new standard for speed and accuracy of printed circuit board (PCB) debug and test.

XJTAG to unveil version 2.0 at Productronica (Hall A1/Stand 448), November 13-16 2007, New Munich Trade Fair Center, Germany
XJTAG v2.0 automates JTAG chain set-up and enables quick and easy categorisation of non-JTAG/cluster devices
New built-in netlist explorer provides a simple interface to view connectivity between devices
Other enhancements include improved memory test, real-time DFT test coverage analysis, an extended library of device-centric test scripts, improved integration with LabVIEW, and support for Xilinx's Virtex-5 FPGA System Monitor
XJTAG, a leading supplier of IEEE Std. 1149.1 compliant boundary scan development tools, today announced version 2.0 of its popular XJTAG boundary scan development system, which sets a new standard for speed and accuracy of printed circuit board (PCB) debug and test.

The new version of the XJTAG system - which is used throughout the electronic product life cycle by board developers and manufacturers to debug, test and program complex Ball Grid Array (BGA) populated printed circuit boards and systems - will be unveiled by XJTAG at Productronica (Hall A1/Stand 448), New Munich Trade Fair Center, Germany, November 13-16, 2007.

Other Mandriva 2008 Packages

cheese

cheese-0.2.4-1mdv2008.0.i586.rpm (667.5 KB)
cheese-0.2.4-1mdv2008.0.src.rpm (737.4 KB)
cheese-debug-0.2.4-1mdv2008.0.i586.rpm (2.3 KB)

Other Mandriva 2006 Packages

dkms-spca5xx-0.60.00-0.1.20060mdk.noarch.rpm (194.4 KB)
dkms-spca5xx-0.60.00-0.1.20060mdk.src.rpm (161.7 KB)

openwengo-0.990-1.4282.1.1.20060mdk.i586.rpm (3.1 MB)

pcb

Pcb is a GPL printed circuit creation tool, currently can be used for production quality pcb's.
Sourceforge: http://sourceforge.net/projects/pcb

Warning! This is a patched version of pcb.

Mandrake/Mandriva Linux RPM's for pcb:

pcb-20080202-1mdv2008.1.i586.rpm (766.5 KB)
pcb-symbols-20080202-1mdv2008.1.i586.rpm (715.5 KB)
pcb-doc-20080202-1mdv2008.1.i586.rpm (1.7 MB)
pcb-elektronist-symbols-20080202-1mdv2008.1.i586.rpm (30.8 KB)
pcb-debug-20080202-1mdv2008.1.i586.rpm (1.4 MB)
pcb-20080202-1mdv2008.1.src.rpm (3.4 MB)

pcb-20080202-1mdv2008.0.i586.rpm (770.7 KB)
pcb-symbols-20080202-1mdv2008.0.i586.rpm (731.3 KB)
pcb-doc-20080202-1mdv2008.0.i586.rpm (1.7 MB)
pcb-elektronist-symbols-20080202-1mdv2008.0.i586.rpm (31.5 KB)
pcb-debug-20080202-1mdv2008.0.i586.rpm (1.5 MB)
pcb-20080202-1mdv2008.0.src.rpm (3.4 MB)

pcb-20070912-2mdv2008.0.i586.rpm (562.7 KB)
pcb-symbols-20070912-2mdv2008.0.i586.rpm (815.6 KB)
pcb-doc-20070912-2mdv2008.0.i586.rpm (1.7 MB)
pcb-elektronist-symbols-20070912-2mdv2008.0.i586.rpm (31.8 KB)
pcb-debug-20070912-2mdv2008.0.i586.rpm (1.3 MB)
pcb-20070912-2mdv2008.0.src.rpm (2.6 MB)

pcb-20070208-2mdv2007.0.i586.rpm (637.1 KB)
pcb-symbols-20070208-2mdv2007.0.i586.rpm (832.1 KB)
pcb-doc-20070208-2mdv2007.0.i586.rpm (1.6 MB)
pcb-elektronist-symbols-20070208-2mdv2007.0.i586.rpm (33.7 KB)
pcb-debug-20070208-2mdv2007.0.i586.rpm (1.2 MB)
pcb-20070208-2mdv2007.0.src.rpm (3.1 MB)

pcb-20060822-1.20060mdk.i586.rpm (562.7 KB)
pcb-symbols-20060822-1.20060mdk.i586.rpm (248.6 KB)
pcb-doc-20060822-1.20060mdk.i586.rpm (1.6 MB)
Light Key
Index - Main Library

Techniques Explained
Design step-by-step
Circuit diagrams
PCB Layout
PCB Etching
Prototyping
Firmware design
Documentation
Manufacturing
Economies of scale
Test Procedures
ECOs - changes

Design Specification
Overview
Specification Intro.
Writing a Spec
Tech Ingredients
Example Specs
Choosing a Designer
R&D Economics
Inspiration

Pictures (=1000 words)
A PCB Factory
Example projects
...more ...more
A real design Lab

Reference, etc
RS232 pinouts
RS485 Autotrax P89LPC932 Past products
Further info
Link library (15k+)
Google search
Google groups

--------------------------------------------------------------------------------

CONTACT or ENQUIRY

--------------------------------------------------------------------------------

?2008 AirBorn The Printed Circuit Board (PCB) Layout
The connections on the PCB should be identical to the circuit diagram, but while the circuit diagram is arranged to be readable, the PCB layout is arranged to be functional, so there is rarely any visible correlation between the circuit and the layout.
PCB layout can be performed manually (using CAD) or in combination with an Autorouter. The best results are usually still achieved using atleast some manual routing - simply because the design engineer has a far better judgement of how to arrange circuitry. Surprisingly, many autorouted boards are often completely illogical in their track routing - the program has optimised the connections, and sacrificed any small amount of order that may have been put in place by manual routing. Generally autorouted boards are slightly harder for a technician to repair or debug, for this reason. Historically, PCBs used to be laid out by drawing or using stick on paper shapes on mylar film, - that really WAS manual routing! between a purpose-built product, such as we deliver, and a general-purpose product such as you might buy from a company like Rabbit. We would label terminals as: "+12v red" "-pwr black" "solenoid+" "solenoid-" whereas competitors may often just give you: "A1 A2 A3 A4". They don't have much of a choice - they have no idea what you will attach to the terminals.

For dense surface mount boards, we often need to leave off component values, and sometimes need to omit the component designators. The silkscreen is the primary method for labelling connectors, replaceable parts, orientation, and even installation notes (for instance "Remove J2 while replacing battery - observe battery polarity")

The PCB layout also needs to take account of EMI and ESD compliance and we have a seperate page on some techniques that we use to get our PCBs to comply. We have a tutorial on designing PCBs - it steps through the CAD process from schematic to layout. We also support the Autotrax/Easytrax CAD package by providing Updated video drivers.

Most of the Etched PCB laminates we produce are:
Double sided Laminate
Two layers of copper tracks, one each side of the board
Plated Through Hole
PTH - each hole is copper plated providing a circuit between sides of the PCB
Fibreglass-resin laminate (FR4)
Solder Mask Over Bare Copper
SMOBC - green insulating ink everywhere except connections
Component legend
Identifying lettering, component outlines and values in white or yellow ink
Tinned
Tinning is application of Solder to all exposed copper, increasing solderability
Hot oil levelled
Hot oil - or hot air - levelling makes the tinning flat, so that surface mount components can be positioned reliably. Visual Fault Analyzer (VFAT) speeds PCB fault Diagnostics and Repair

Easy-to-Use Graphical Fault Viewer lowers BGA re-work costs

San Jose, CA. February 21, 2000. Intellitech Corporation, the technology leader in scan-based debug and test, announced today the availability of the Visual Fault Analyzer (VFAT) for viewing and identifying PCB (printed circuit board) assembly faults. VFA is a new generation application that works with Intellitech's PCB ATE (Automatic Test Equipment) that speeds diagnostics and repair by visually showing where the faults are located. Previously, when performing PCB assembly tests, interconnect faults such as stuck-at faults, shorts and opens were diagnosed with text messages, displaying net connectivity information. VFA augments text based diagnostics by visually displaying the diagnostic information onto an image of the Unit-Under-Test (UUT).

The VFA user interface integrates an advanced graphical viewing capability of the UUT with the text diagnostic message output. It provides design and test engineers with the ability to visually analyze fault diagnostic data on a display of the physical UUT. Users now have failure information available that is based on the physical placement, etch routing and layout of components, interconnects and VIAs (a VIA is a small hole used to connect copper etch from one layer of the PCB to another layer). Viewing the fault information in this way allows isolation and diagnosis of faults to be made quickly and easily. Plain text output doesn't include information about the PCB's VIA's which contribute to the faults in a large number of cases. Users can readily see the relationship between the logical fault diagnosis and the real manufacturing defects of the physical design.

"You can diagnose faults much faster and easier with VFA", said Mike Ricchetti, Chief Technology Officer of Intellitech Corporation. "The VFA enables users to pinpoint difficult to find VIA-to-VIA solder bridges and pin-to-VIA shorts, that plain text based diagnostics can't solve. It really excels with SMT (Surface Mount Technology) as this technology requires VIA's to connect the surface mount pads with the other PCB layers. We've found that VIA's contribute to a large number of the faults.

Click here if you would like to see the Visual Fault Analyzer in action! Title:Accelerating PCB development and debug in advance of platform ASIC prototype samples Document Type and Number:United States Patent 7363608
Abstract:A system and method are provided for accelerating development and debug of a printed circuit board (PCB) designed for use with a platform ASIC in advance of availability of a prototype sample of the platform ASIC. Aspects of the invention include a pin-out adapter card that implements a predefined pin-out of the ASIC and that hosts FPGA logic resources for emulating I/O functionality and some (or all) of the ASIC core logic; a PCB designed for use with the platform ASIC, wherein the PCB includes the predefined ASIC pin-out for eventually mating with the ASIC; and a socket having mating connectors on both sides for mating with the ASIC pin-out on the PCB and to the ASIC pin-out on the adapter card, respectively, for coupling the adapter card to the PCB, thereby enabling development and debug of the PCB prior to availability of ASIC samples.